1. Field of the Invention
Generally, the present disclosure relates to the fabrication of integrated circuits, and, more particularly, to transistors having strained channel regions by using embedded semiconductor alloys, such as silicon/germanium, to enhance charge carrier mobility in the channel regions of the transistors.
2. Description of the Related Art
The fabrication of complex integrated circuits requires the provision of a large number of transistor elements, which represent the dominant circuit element for complex circuits. For example, several hundred millions of transistors may be provided in presently available complex integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, MOS technology is the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. In MOS circuits, field effect transistors, i.e., P-channel transistors and/or N-channel transistors, are used for forming circuit elements, such as inverters and other logic gates to design highly complex circuit assemblies, such as CPUs, storage chips and the like. During the fabrication of complex integrated circuits using MOS technology, transistors are formed on a substrate including a crystalline semiconductor layer. A MOS transistor or generally a field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers, and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. For example, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the drain and source regions so as to provide low sheet and contact resistivity in combination with desired channel controllability. Moreover, the gate dielectric material may also be adapted to the reduced channel length in order to maintain the required channel controllability. However, some mechanisms for maintaining high channel controllability may also have a negative influence on the charge carrier mobility in the channel region of the transistor, thereby partially offsetting the advantages gained by the reduction of the channel length.
Since the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the new development of highly complex process techniques and may also contribute to less pronounced performance gain due to mobility degradation, it has been proposed to enhance the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby enabling a performance improvement that is comparable with the advance to a technology standard requiring extremely scaled critical dimensions, while avoiding or at least postponing many of the process adaptations associated with device scaling.
One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance by creating tensile or compressive stress in the vicinity of the channel region so as to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region for a standard crystallographic configuration of the active silicon material, i.e., a (100) surface orientation with the channel length aligned to the <110> direction, increases the mobility of electrons, which in turn may directly translate into a corresponding increase in conductivity. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. The introduction of stress or strain engineering into integrated circuit fabrication is an extremely promising approach, since strained silicon may be considered as a new type of semiconductor material, which may enable the fabrication of fast powerful semiconductor devices without requiring expensive semiconductor materials, while many of the well-established manufacturing techniques may still be used.
Consequently, it has been proposed to introduce, for instance, a silicon/germanium (Si/Ge) material next to the channel region so as to induce a compressive stress that may result in a corresponding strain. When forming the Si/Ge material, the drain and source regions of the PMOS transistors are selectively recessed to form cavities, while the NMOS transistors are masked, and subsequently the silicon/germanium material is selectively formed in the cavities of the PMOS transistor by epitaxial growth.
Although this technique provides significant advantages in view of performance gain of P-channel transistors and thus of the entire CMOS device, it turns out that, upon further device scaling, the efficiency of this strain-inducing mechanism strongly depends on the strain level in the semiconductor alloy and, in particular, from the lateral offset of the strain-inducing material from the channel region. That is, the strain-inducing effect is based on the fact that a semiconductor alloy has a different natural lattice constant compared to the silicon base material, such that the strain-inducing semiconductor alloy, such as the silicon/germanium material, is grown in a strained state, which in turn induces the desired strain in the laterally adjacent channel region. The magnitude of the strain thus depends on the amount of the lattice mismatch between the natural lattice constants of silicon and the semiconductor alloy. Consequently, increasing the fraction of the atomic species having a different covalent radius compared to the silicon species may thus result in an increased strained state. It turns out, however, that, for presently-available selective epitaxial growth techniques for silicon/germanium material, the maximum germanium concentration may be limited at approximately 80 atomic percent, unless severe lattice defect may be created during the selective epitaxial growth process. Moreover, the amount of the strain-inducing semiconductor material, and in particular its lateral offset, which may be considered as the lateral offset with respect to an electrode material of the gate electrode structure, may thus also significantly influence the finally-obtained strain level in the underlying channel region.
Due to the above-specified restrictions of currently available deposition recipes, as discussed above, great efforts are being made in reducing the lateral offset of the strain-inducing semiconductor material and also increasing the amount of material positioned in the drain and source areas of the transistor. Basically, the amount of strain-inducing semiconductor material may be increased, for instance, increasing the size and appropriately selecting the shape of the corresponding cavities that are formed laterally offset from the gate electrode structure. To this end, sophisticated etch strategies are applied, wherein the etch depth may substantially determine the size and thus the amount of semiconductor material that may be formed therein. To this end, corresponding anisotropic plasma-based etch processes are applied, wherein, however, the lateral offset may basically be determined by the width of any protecting spacer or liner materials formed on the sidewalls of the gate electrode structure in order to maintain integrity of sensitive gate materials. Although generally an offset of zero may be established by providing extremely thin protective liner materials, any such process recipes may result in significant variability of transistor characteristics, since extremely thin protective materials may have to be deposited, wherein any fluctuations in the process strategies involved may thus contribute to increased variations of the lateral distance, since, in particular, also any variations of the plasma-based etch process may additionally significantly contribute to corresponding variations of the resulting cavities.
Consequently, in other approaches, it has been proposed to provide a certain degree of under-etching, for instance by implementing an isotropic etch phase, which may thus provide a lateral etch rate, thereby obtaining a negative offset of the resulting cavities. In order to reduce any process-related variations of the under-etched cavities, frequently crystallographically anisotropic etch recipes are applied, in which the etch rate in one crystallographic plane is significantly less than in other crystallographic planes, so that the lattice planes of reduced etch rate may act as efficient etch stop planes. For example, for silicon material, a plurality of wet chemical etch recipes are well established in which the (111) planes may act as efficient etch stop planes, thereby enabling a well-controlled etch process, in particular in the lateral direction, which thus has a self-limiting behavior, thereby resulting in superior process control with respect to size and shape of the cavities. Consequently, the strain-inducing semiconductor alloy, such as the silicon/germanium alloy, may be filled in to the previously formed cavities of well-defined shape and size, thereby obtaining a high strain transfer into the channel region while reducing any process-related fluctuations, in particular any fluctuations of the etch process.
Consequently, according to these process strategies, a pronounced degree of under-etching may be accomplished in a well-controllable manner by using crystallographically anisotropic etch techniques, which may thus enable a significant increase of the finally-obtained strain in the channel region. Thus, in some approaches, the degree of under-etching of the gate electrode structure upon forming the cavities in the active region of, for instance, P-channel transistors, has been increased in an attempt to further enhance transistor performance. It turns out, however, that upon further increasing the extension of the cavities below the gate electrode structure, a significant mechanical instability is introduced, which may result in severe transistor deterioration or even in a complete transistor failure upon forming the strain-inducing semiconductor alloy and completing the basic transistor configuration by forming drain and source regions.
In view of the situation described above, the present disclosure relates to techniques and semiconductor devices in which, generally, transistor characteristics may be adjusted on the basis of epitaxially-grown semiconductor materials, which may be provided with a reduced offset or a negative off-set with respect to the gate electrode material, while avoiding or at least reducing the effects of one or more of the problems identified above.